The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
Status: PublishedPublication date: 2004-12
Edition: 1Number of pages: 405
Technical Committee: ISO/IEC JTC 1/SC 25 Interconnection of information technology equipment
- ICS :
- 35.100.30 Network layer
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