Specifies the logical layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. Intended to be used as a component within a profile to build systems with higher levels of compatibility.

General information

  • Status :  Withdrawn
    Publication date : 1994-12
  • Edition : 1
    Number of pages : 208
  • :
    Information technology
  • 35.160
    Microprocessor systems

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